`timescale 1ns/1ns
`define halfperiod 10
module sequential_detector_tb ();
    
reg [31:0] data;
reg clk,rst_n;
wire in,out;

sequential_detector sequential_detector_tb
(
    .clk(clk),
    .rst_n(rst_n),
    .in(in),
    .out(out)
);

initial begin
    clk = 0;
    rst_n = 1;
    #5 rst_n = 0;
    #10 rst_n = 1;
    // data = 24'b0011_0010_1011_0010_1001_0010;
    data = 32'b0000_1100_1010_1100_1010_1100_1100_1010;
    // #(`halfperiod * 100) $stop;
end

always #`halfperiod clk = ~clk;

always @(negedge clk) begin
    #5 data = {data[30:0], data[31]};
end
assign in = data[31];

endmodule